Information

ULSIWS2017 is to be held in Novi Sad, Republic of Serbia. See you next year!!

Student Poster Award

Winners of Excellent Student Poster Award: Sha Tao (Royal Institute of Technology, Sweden), and Yuki Tabata (Tohoku University, Japan)

General Chair, Dr. H. Nakahara, Prof. T. Hanyu (Adviser of Y. Tabata), Ms. Sha Tao, Mr. Y. Tabata, and Prof. E. Dubrova (Adviser of S. Tao). The photo is provided by Prof. Yasushi Yuminaka, Gunma Univ., Japan.

The 25th International Workshop on Post-Binary ULSI Systems (ULSIWS) will be held in conjunction with the IEEE 46th Annual International Symposium on Multiple-Valued Logic (ISMVL2016) on May 17, 2016 in Hokkaido, Japan. You are invited to submit an original paper, survey or tutorial paper on any subject in the area of new devices for ULSI systems, high-performance circuits and design, and new LSI architecture. Proposals for special sessions concerning the above topics are also welcome.

Updates

  • Final program [PDF file] has been updated (May 12, 2016)
  • Tentative program has been updated (May 2, 2016)
  • Workshop venue has been updated (Feb. 23, 2016)
  • Prof. Wille and Prof. Anderson were confirmed as invited speakers (Feb. 23, 2016)
  • Prof. Waho was confirmed as invited speakers (Jan. 14, 2016)
  • Post-Binary ULSI Workshop 2016 Website opened (Sep. 1, 2015)

Important Dates

Venue and Accommodation

The symposium venue is take place at the Frontier Research in Applied Science Building at Hokkaido University, that is the same of the ISMVL2016 (http://www.oia.hokudai.ac.jp/maps/?id=133). For more detail, please see ISMVL2016 venue information.

Final Program [PDF]

Invited Talk

We are proud to announce invited speakers.
  • Prof. Jason Anderson (University of Toronto, Canada)
  • Title: Synthesizing Circuits from Software
  • Biography:
    Jason Anderson (http://janders.eecg.toronto.edu) received the B.Sc. degree in computer engineering from the University of Manitoba, and the M.A.Sc. and Ph.D. degrees in electrical and computer engineering (ECE) from the University of Toronto (U of T). He is an Associate Professor with the Department of ECE, U of T and holds the Jeffrey Skoll Endowed Chair in Software Engineering. From 1997-2008, he was with the field-programmable gate array (FPGA) implementation tools group at Xilinx, Inc. Prof. Anderson has received six awards for excellence in undergraduate teaching, four best papers awards, holds 27 U.S. patents, and has authored over 70 papers in refereed international journals and symposia. His research interests include all aspects of computer-aided design (CAD), architecture and circuits for FPGAs. Since 2009, he has been leading the LegUp open-source high-level synthesis (HLS) project (http://legup.eecg.toronto.edu), which allows a C-langage program to be automatically synthesized into a hardware circuit implemented on an FPGA. LegUp HLS has been downloaded by over 2000 users worldwide. Dr. Anderson was General Chair for the 2015 IEEE Int'l Conference on Application-specific Systems, Architectures and Processors (ASAP). He will be Program Co-Chair for the 2016 Int’l Conference on Field-Programmable Logic and Applications (FPL) and Program Chair for the 2017 ACM Int’l Symposium on Field-Programmable Gate Arrays.
  • Prof. Robert Wille (Johannes Kepler University Linz, Austria)
  • Title: Reversible Logic: What's next?
  • Abstract:
    Reversible logic received significant interest in the past years -- particularly, in the ULSIWS/MVL community. This eventually led to many contributions on how to efficiently design and apply reversible circuits. At the same time, many open problems and unused potential are left to be solved and exploited, respectively. This talk provides a brief review of reversible logic and gives an overview on the recent accomplishments. Based on that, it aims for starting a discussion on "What's next?", i.e. what research tasks should we tackle in the near future. To this end, explicit suggestions will be made which (hopefully) will be controversially discussed during the talk.
  • Prof. Takao Waho (Sophia University, Japan)
  • Title: Analog-to-Digital Converters Using Artificial Neural Network: A Review
  • Biography:
    Dr. Takao Waho received the B. S., M. S., and Ph. D. degrees in Physics from Waseda University, Tokyo, Japan, in 1973, 1975 and 1978. In 1975, he joined Musashino Electrical Communications Laboratories, Nippon Telegram and Telephone Public Corporation (now NTT), where he investigated III-V compound semiconductor device technology and circuit applications. Since 1999, he has been a Professor of the Faculty of Science and Technology, Sophia University, Tokyo. His current research interest includes CMOS analog IC design, nanostructure semiconductor devices and their applications; in particular, analog-to-digital converters, delta-sigma modulators, and multi-valued logic circuits. He received the Distinctive Contribution Paper Award and Certificate of Appreciation from the IEEE Computer Society in 1996 and 2009, respectively. Dr. Waho served as Editor of the IEICE Transactions on Electronics (Japanese Edition), as Technical Committee Chairs of IEICE Electron Devices and IEEE Computer Society Multiple-Valued Logic, and as General Chairs of the Topical Workshop on Heterostructure Microelectronics (TWHM) held in Nagano, Japan, in August 2011, and of the IEEE International Symposium on Multiple-Valued Logic (ISMVL) held in Toyama, Japan, in May 2013.

Call for Papers and Sessions

You are invited to submit an original paper, survey or tutorial paper on any subject in the area of new devices for ULSI systems, high-performance circuits and design, and new LSI architecture. The topics of interest include but not limited to:

  • Algebra and Formal Aspects
  • ATPG and SAT
  • Automatic Reasoning
  • Bio-Inspired and Novel
  • Hardware Algorithms
  • Communication Systems
  • Computer Arithmetic
  • Computer Security
  • Data Bases
  • Data Mining
  • Decision Diagram
  • Fuzzy Logic and Soft Computing
  • Image Processing
  • Logic Design and Switching Theory
  • Logic Programming
  • Machine Learning and Robotics
  • Mathematical Fuzzy Logic
  • Medical and Wellness Care Technology
  • Nano Technology and Computer Security
  • Opto-Electronics
  • Index Generation Functions
  • Quantum Computing
  • Quantum Cryptography
  • Quantum Devices
  • Signal Processing
  • Single Electrons
  • Spectral Techniques
  • Superconductivity
  • Web Intelligence
  • Verification
  • Philosophical Aspects

Proposals for special sessions concerning the above topics are also welcome. Special session proposals should be submitted to the General Chair Hiroki Nakahara.

The workshop has regular sessions as well as a Student Poster Session for students to present their research work in progress. Details will be announced.



Submission Guidelines

Please submit one-page abstract according to the following instruction:
  • Please convert the manuscript file into a PDF file using the Adobe Acrobat Distiller. All fonts used in the manuscript must be embedded in the PDF file in converting.
  • Please send the PDF file via e-mail to nakahara{at}cs.ehime-u.ac.jp.
  • If you cannot convert it into a PDF file, please send three copies of the manuscript printed in A4 paper with a cover page via postal mail to:

    Hiroki Nakahara,
    Ehime University, Bunkyou-cho 3, Matsuyama, Ehime, 790-8577, JAPAN

Final Submission

Authors are requested to submit the final camera-ready manuscript upon acceptance. Please prepare the camera-ready manuscript according to the following guideline.

Paper Format

  1. Paper Size
    The manuscript should be clearly printed on single-sided A4 (210mm x 297mm) or US letter (8.5 x 11 inch) paper.
  2. Margins
    The left and right margins are the same and are to be 25mm. The top and bottom margins are to be 30mm and 25mm, respectively.
  3. Language
    All papers must be written in English.
  4. Restriction on the Number of Pages
    The number of pages for a manuscript is not strictly restricted. But, 6 to 8 pages for Regular Sessions are preferred.
  5. Page Numbering
    Please do not type page numbers on the camera-ready manuscript.
  6. Details
    We recommend you use the IEEE format to prepare your camera-ready manuscript. You can get the Microsoft Word style file and LaTeX style files.

    MS Word style file: MS Word Template file
    LaTeX style files: For Linux/Unix, IEEEtran.tar.gz
    For PC and Mac, IEEEtran.zip

Important Date

  • March 1, 2016: Proposal of Special Session due
  • March 14, 2016: Notification of Special Session
  • April 1, 2016: Submission of Abstract due
  • April 7, 2016: Notification of Paper Acceptance
  • April 21, 2016: Submission of Final Papers due

  • Registration (Note, be subject to change)

    • Registration fee is free.
    • To all participants who make a registration in advance, the conference proceedings will be distributed and light meals will be served for lunch.
    • To make a pre-registration please send email notification to Hiroki Nakahara (nakahara{at}cs.ehime-u.ac.jp) by (TBD).
    • On-site registration will be accepted, but we cannot guarantee your proceeding and lunch service.
    For additional information contact: Hiroki Nakahara, nakahara{at}cs.ehime-u.ac.jp

    Committee

    The ULSIWS2016 is organized by follwoing members. If you have questions, do not hesitate to contact us. Best way to reach us is via mail.

    General Chair:

    • Hiroki Nakahara,nakahara{at}cs.ehime-u.ac.jp

    Local Arrangement

    • Mayuka F. Kawaguchi, mayuka{at}ist.hokudai.ac.jp